Supercomputers surpass 2.5 petaflops

The biannual list of the world's fastest supercomputers was released on November 13, 2010. For the first time, supercomputing capability surpassed 2.5 petaflops with the world's fastest supercomputer, the Tianhe-1A - NUDT TH MPP, X5670 2.93Ghz 6C, NVIDIA GPU, FT-1000 8C NUDT, at the National Supercomputing Center in Tianjin China, clocking in at over 2.5 petaflops.

Figure 1 illustrates how supercomputing power has been growing in the last five years, starting at (a paltry) 136.8 gigaflops in June 2005, and experiencing four solid doublings in growth. This rate of progress is estimated to continue, and usher in the exaflop era of supercomputing by mid-decade. The IBM Roadrunner at Los Alamos was the first to achieve speeds over one petaflop in June 2008 and held onto the fastest computer seat for three measurement periods, then was surpassed by the Cray Jaguar at Oakridge for two measurement periods. China has now captured the fastest supercomputer ranking with its NUDT MPP.

Figure 1. Growth in Supercomputing Capability: Jun 2005 - Nov 2010

Source: Top 500 Supercomputing Sites List Releases

The world's supercomputers are working on many challenging problems in areas such as physics, energy, and climate modeling. A natural question arises as to how soon human neural simulation may be conducted with supercomputers. It is a challenging problem since neural activity has a different architecture than supercomputing activity. Signal transmission is different in biological systems, with a variety of parameters such as context and continuum determining the quality and quantity of signals. Distributed computing systems might be better geared to processing problems in a fashion similar to that of the brain. The largest current project in distributed computing, Stanford protein Folding@home, reached 5 petaflops in computing capacity in early 2009, just as supercomputers were reaching 1 petaflop. The network continues to focus on modeling protein folding but could eventually be extended to other problem spaces.

Semiconductor roadmap updates

The working group documents and presentations are now available from the most recent International Technology Roadmap for Semiconductors (ITRS) 2009 Winter Conference held December 16, 2009 in Hsinchu City, Taiwan.

One of the most important updates from the ITRS 2009 meeting is a shift out in the time scale for the next expected computing nodes. There is a focus on both FLASH memory ½ pitches and the usual DRAM ½ pitches as smaller nodes are expected to be achieved with FLASH before DRAM. Specifically for FLASH, 22 nm is estimated for 2013, 16 nm in 2016 and 11 nm in 2019. For DRAM, 32 nm is estimated for 2013, 22 nm in 2016, and 16 nm in 2019.

An important architectural shift is underway for packing more transistors onto chips: moving from planar to multidimensional architectures. Another big industry focus is in implementing 450 mm wafers for chip manufacturing, up from the 300 mm current standard. (Figure 1)

Figure 1: One of the world's first 450 mm wafers

In lithography, a key bottleneck area, the two main technologies that will probably be in use for the current and next few nodes are Extreme Ultraviolet Lithography (EUV) and 193 nm immersion half pitch Double Patterning. EUV is less expensive. For later nodes (22 nm, 16 nm, and 11 nm), EUV and double patterning, together with ML2 (maskless lithography), imprinting, directed self-assembly, and interference lithography may be used.

An important challenge is the top-down (traditional engineered electronics) meets bottom-up (evolved molecular electronics) issue of how nodes 15 nm and smaller will be designed given quantum mechanics. The Emerging Research Devices (ERD) and Emerging Research Materials (ERM) working groups presented some innovative solutions, however the majority of the roadmap focus is on the nearer term, the next couple of nodes.