Semiconductor roadmap updates

The working group documents and presentations are now available from the most recent International Technology Roadmap for Semiconductors (ITRS) 2009 Winter Conference held December 16, 2009 in Hsinchu City, Taiwan.

One of the most important updates from the ITRS 2009 meeting is a shift out in the time scale for the next expected computing nodes. There is a focus on both FLASH memory ½ pitches and the usual DRAM ½ pitches as smaller nodes are expected to be achieved with FLASH before DRAM. Specifically for FLASH, 22 nm is estimated for 2013, 16 nm in 2016 and 11 nm in 2019. For DRAM, 32 nm is estimated for 2013, 22 nm in 2016, and 16 nm in 2019.

An important architectural shift is underway for packing more transistors onto chips: moving from planar to multidimensional architectures. Another big industry focus is in implementing 450 mm wafers for chip manufacturing, up from the 300 mm current standard. (Figure 1)

Figure 1: One of the world's first 450 mm wafers

In lithography, a key bottleneck area, the two main technologies that will probably be in use for the current and next few nodes are Extreme Ultraviolet Lithography (EUV) and 193 nm immersion half pitch Double Patterning. EUV is less expensive. For later nodes (22 nm, 16 nm, and 11 nm), EUV and double patterning, together with ML2 (maskless lithography), imprinting, directed self-assembly, and interference lithography may be used.

An important challenge is the top-down (traditional engineered electronics) meets bottom-up (evolved molecular electronics) issue of how nodes 15 nm and smaller will be designed given quantum mechanics. The Emerging Research Devices (ERD) and Emerging Research Materials (ERM) working groups presented some innovative solutions, however the majority of the roadmap focus is on the nearer term, the next couple of nodes.